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S3C8465/c8469/p8469 product overview 1 - 1 1 product overview sam8 product family samsung's new sam8 family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. a dual address/data bus architecture and a large number of bit- or nibble-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included to support real-time operations. many sam8 microcontrollers have an external interface that provides access to external memory and other peripheral devices. a sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum six cpu clocks) can be assigned to one interrupt level at a time. S3C8465/c8469 microcontroller the S3C8465/c8469 single-chip 8-bit microcontroller is designed for useful 10-bit resolution a/d converter, uart, sio, zcd extended pwm application field. its powerful sam8 7 cpu architecture includes . the internal register file is logically expanded to increase the on-chip register space. the S3C8465/c8469 has 16 /32 k bytes of on-chip program rom. a sophisticated bus interface enables access to external memory and other peripherals when you use the chip in rom-less mode. following samsung's modular design approach, the following peripherals are integrated with the sam8 7 core: ? large number of programmable i/o ports (total 56 pins) ? one asynchronous uart module ? one synchronous sio module ? analog-to-digital converter with eight input channels and 10 -bit resolution ? one 8-bit basic timer for watchdog function ? one 8-bit timer/counter with three operating modes (timer 0) ? one 8-bit timer for zero-cross detection circuit (timer 2) ? two general-purpose 16-bit timer/counters with four operating modes (timer module 1) ? pwm block with one capture module, 16-bit timer/counter, pwm extension mode, and two pwm outputs ? one zero cross detection module the S3C8465/c8469 is a versatile general-purpose microcontroller that is ideal for use in a wide range of electronics applications requiring complex timer/counter, pwm, capture, sio, uart and zcd functions. it is available in a 64- pin sdip or 64-pin qfp package. otp the s3p8469 is an otp (one time programmable) version of the S3C8465/c8469 microcontroller. the s3p8469 microcontroller has an on-chip 32-kbyte one-time-programmable eprom instead of a masked rom. the s3p8469 is comparable to the S3C8465/c8469, both in function and in pin configuration.
product overview S3C8465/c8469/p8469 1 - 2 features cpu ? sam8 7 cpu core memory ? 528 -byte general purpose register area ? 16 /32 k - byte internal program memory ? rom-less operating mode external interface ? 64 k - byte external data memory area ? 64 k - byte external program memory area (rom-less mode) instruction set ? 79 instructions ? idle and stop instructions added for power-down modes instruction execution time ? 500 ns at 12 mhz f osc (minimum) interrupts ? 2 1 interrupt sources and 2 1 vectors ? eight interrupt levels ? fast interrupt processing general i/o ? seven i/o ports (total 56 pins) ? s even bit-programmable ports pwm and capture ? two 14-bit pwm output ? one capture serial i/o ? one synchronous serial i/o module ? selectable transmit and receive rates ? selectable baud rate for rx and tx respectively timer/counters ? one 8-bit basic timer for watchdog function ? one 8-bit timer/counter with three operating modes (timer 0) ? one 8-bit timer for the zero-cross detection circuit ? two 16-bit general-purpose timer/counters with fou r operating modes (timer c and d) uart ? one uart module ? full duplex serial i/o interface with three uart modes a/d converter ? eight analog input pins ? 10 -bit conversion resolution ? 2 0 s conversion time ( 10 mhz cpu clock) zero cross detection circuit ? zero cross detection circuit that generates a digital signal in synchronization with an ac signal input buzzer frequency output ? 200 hz to 20 khz signal can be generated oscillator frequency ? 1 mhz to 12 mhz external crystal oscillator ? maximum 12 mhz cpu clock operating temperature range ? ? 4 0 c to + 85 c operating voltage range ? 2.7 v to 5.5 v package types ? 64-pin sdip, 64-pin qfp
S3C8465/c8469/p8469 product overview 1 - 3 block diagram port i/o and interrupt control sam8 cpu basic timer port 1 port 0 port 0 p0.0-p0.7 (a8-a15) 16/32-kbyte rom 528-byte register file p3.0-p3.7 port 3 p4.0/int4- p4.7/int11 port 4 p5.0-p5.7 port 5 p6.0-p6.7 port 6 adc0 -adc7 adc txd rxd uart sio pwm/ cap timers c and d tcg x out x in osc t0 t0ck timer tcck tdck tdg pwm1 capa pwm0 so sck si sam8 bus p1.0-p1.7 (ad0-ad7) p2.0-p2.3 p2.4/zcd-p2.7/int3 figure 1-1 . block diagram
product overview S3C8465/c8469/p8469 1 - 4 pin assignments p0.7/a15 p0.6/a14 p0.5/a13 p0.4/a12 p0.3/a11 p0.2/a10 p0.1/a9 p0.0/a8 p4.7/int11/tdg p4.6/int10/tcg p4.5/int9/tdck p4.4/int8/tcck p4.3/int7/capa p4.2/int6 p4.1/int5/rxd v dd v ss x out x in ea p4.0/int4 p3.7/txd reset p3.6/so p3.5/si p3.4/ sck p3.3/t0ck p3.2/t0 p3.1/pwm1 p3.0/pwm0 p2.7/int3 p2.6/int2 S3C8465 s3c8469 64-sdip-750 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p1.0/ad0 p1.1/ad1 p1.2/ad2 p1.3/ad3 p1.4/ad4 p1.5/ad5 p1.6/ad6 p1.7/ad7 p5.7/adc7 p5.6/adc6 p5.5/adc5 p5.4/adc4 p5.3/adc3 p5.2/adc2 p5.1/adc1 p5.0/adc0 av ss av ref p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p6.0 p2.0/ as p2.1/ ds p2.2/r/ w p2.3/ dm p2.4/zcd p2.5/buz 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 figure 1-2 . pin assignment diagram (64-sdip)
S3C8465/c8469/p8469 product overview 1 - 5 p0.0/a8 p4.7/int11/tdg p4.6/int10/tcg p4.5/int9/tdck p4.4/int8/tcck p4.3/int7capa p4.2/int6 p4.1/int5/rxd v dd v ss x out x in ea p4.0/int4 p3.7/txd reset p3.6/so p3.5/si p3.4/ sck S3C8465/c8469 64-qfp-1420f (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p0.1/a9 p0.2/a10 p0.3/a11 p0.4/a12 p0.5/a13 p0.6/a14 p0.7/a15 p1.0/ad0 p1.1/ad1 p1.2/ad2 p1.3/ad3 p1.4/ad4 p1.5/ad5 64 63 62 61 60 59 58 57 56 55 54 53 52 p3.3/t0ck p3.2/t0 p3.1/pwm1 p3.0/pwm0 p2.7/int3 p2.6/int2 p2.5/buz p2.4/zcd p2.3/ dm p2.2/r/ w p2.1/ ds p2.0/ as p6.0 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p1.6/ad6 p1.7/ad7 p5.7/adc7 p5.6/adc6 p5.5/adc5 p5.4/adc4 p5.3/adc3 p5.2/adc2 p5.1/adc1 p5.0/adc0 av ss av ref p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 figure 1-3 . pin assignment diagram (64-pin qfp package)
product overview S3C8465/c8469/p8469 1 - 6 table 1- 1. S3C8465/c8469 pin descriptions pin name pin type pin description circuit number pin number share pins p0.0?p0.7 i/o bit-programmable i/o port for schmitt trigger input or push-pull, open-drain, output. pull-up resistors are assignable by software. port 0 can also be configured as external interface address line a8?a15 1 8?1 (1 , 64 ? 5 8) ? a8?a15 p1.0?p1.7 i/o same general characteristics as port 0. port 1 can also be configured as external interface address/data lines ad0?ad7 1 6 4 ?5 7 ( 57 ? 50 ) ? ad0?ad7 p2.0?p2.3 p2.4?p2.7 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. p2.0?p2.3 can be configured for external bus control signals. p2.4?p2.7 are used for general i/o or for the zcd, buz, int2 and int3 2 3 38 ? 35 ( 31 ? 28 ) 34 ? 31 ( 27 ? 24 ) ? as, ds dm, r/w zcd, buz int2, int3 p3.0?p3.7 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. each port 3 pin has an alternative function: p3.0: pwm0 (pwm0 module output) p3.1: pwm1 (pwm1 module ouptut) p3.2: t0 (t0 capture input or pwm output) p3.3: t0ck (timer 0 external clock input) p3.4: sck (sio module input ) p3.5: si (sio module clock i/o) p3.6: so (sio module output) p3.7: txd : so1 (the t0 function for p3.2 is selected using the t0con register.) 4 30 ? 22 ( 23 ? 15 ) (see pin description) p4.0?p4.7 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. port 4 pins are used external interrupts int4?int11 or for the following share functions: p4.1: rxd ( uart module input ) p4.3: cap a (capture input) p4.4: tcck (timer/counter c clock input) p4.5: tdck (timer/counter d clock input) p4.6: tcg (timer c gate input) p4.7: tdg (timer d gate input) 5 21, 15 ?9 ( 14 ? 2 ) (see pin description)
S3C8465/c8469/p8469 product overview 1 - 7 table 1- 1. S3C8465/c8469 pin descriptions (continued) pin name pin type pin description circuit number pin number share pins p5.0?p5.7 i/o bit-programmable i/o port for schmitt trigger input or push-pull, output. pull-up resistors are assignable by software. port 5 pins can also be used as a/d converter inputs. 6 49 ?5 6 ( 42 ? 49 ) adc0? adc7 p6.0?p6.7 i/ o individual pins are software configurable as input or push-pull, open-drain, output. pull-up resistors are assignable by software. 1 39 ?4 6 ( 32 ? 39 ) ? ad0?ad7 i/o external interface address/data line 6 64?57 (57?50) p1.0?p1.7 as ds r/ w dm i/o external bus control signals 2 38?35 (31?28) p2.0?p2.3 zcd i/o zero cross detector input 2 34 (27) p2.4 buz i/o 200 hz?20 khz frequency output for buzzer sound 2 33 (26) p2.5 pwm0 pwm1 i/o pwm output 3 30, 29 (23, 22) p3.0?p3.1 t0 (cap) i/o t0 capture input or pwm output 3 28 (21) p3.2 t0ck i/o external clock input for timer 0 3 27 (20) p3.3 sck i/o sio clock signal 3 26 (19) p3.4 si, so i/o sio data input/output 3 25, 24 (18, 17) p3.5?p3.6 txd i/o uart data output 3 22 (15) p3.7 int2?int3 i/o external interrupts: the triggering edge is selectable. 2 32, 31 (25, 24) p2.6?p2.7 int4 i/o external interrupts: the triggering edge is selectable. 4 21 (14) p4.0 rxd/int5 i/o uart data input or external interrupt: the triggering edge is selectable. 4 15 (8) p4.1 int6 capa/int7 i/o capture module input or external interrupt: the triggering edge is selectable. 4 14,13 (7, 6) p4.2?p4.3
product overview S3C8465/c8469/p8469 1 - 8 table 1- 1. S3C8465/c8469 pin descriptions (concluded) pin name pin type pin description circuit number pin number share pins tcck/int8 tcdk/int9 i/o timer/counter c and d clock input or external interrupts: the triggering edge is selectable. 4 12, 11 (5, 4) p4.4?p4.5 tcg/int10 tdg/int11 i/o timer/counter c and d clock input or external interrupts: the triggering edge is selectable. 4 10, 9 (3, 2) p4.6?p4.7 adc0? adc7 i/o a/d converter inputs 5 49?56 (42?49) p5.0?p5.7 x in , x out ? system clock input and output pins ? 19 , 18 ( 12 , 11 ) ? reset i system reset pin 7 23 (1 6 ) ? ea i external access (ea) pin with three modes: 0 v: normal operation (internal rom) 5 v: rom-less operation (external interface) 12.5 v: otp read/write mode ? 20 ( 13 ) ? av ref , av ss ? a/d converter reference voltage input and ground ? 47 , 48 ( 40 , 41 ) ? v dd ,v ss ? voltage input pin and ground ? 16 , 17 ( 9 , 10 ) ? note : pin numbers shown in parentheses " ( ) " are for the 64-pin qfp package.
S3C8465/c8469/p8469 product overview 1 - 9 pin circuits table 1- 2. pin circuit assignments for the S3C8465/c8469 circuit number circuit type S3C8465/c8469 assignments 1 i/o port 0 ,1 and port 6 2 i/o port 2 (p2.0?p2.3 only) 3 i/o port 2 (p2.4?p2.7 only) 4 i/o port 3 5 i/o port 4 6 i/o port 5 7 i reset note : diagrams of circuit types 1? 7 are presented below.
product overview S3C8465/c8469/p8469 1 - 10 v dd open-drain in/out in output disable pull-up resistor (typical value: 47 k w ) v dd data pull-up enable figure 1- 4. pin circuit type 1 (port 0 ,1 and port 6 ) v dd pull-up resistor (typical value: 47 k w ) v dd pull-up enable external interface ( as , ds , r/ w , dm ) port 2 (low byte) data m u x select in output disable in/out data figure 1-5 . pin circuit type 2 (port 2, p2.0?p2.3 only)
S3C8465/c8469/p8469 product overview 1 - 11 external interrupt input v dd pull-up resistor (typical value: 47 k w ) v dd pull-up enable control output (buz) port 2 (high byte) data m u x select output disable in/out noise filter normal input zcd input figure 1-6 . pin circuit type 3 (port 2, p2.4?p2.7 only)
product overview S3C8465/c8469/p8469 1 - 12 v dd pull-up resistor (typical value: 47 k w ) v dd pull-up enable control output port 3 m u x select normal input output disable in/out data figure 1-7 . pin circuit type 4 (port 3) external interrupt input v dd pull-up resistor (typical value: 47 k w ) v dd pull-up enable data output disable in/out noise filter alternative input normal input figure 1-8 . pin circuit type 5 (port 4)
S3C8465/c8469/p8469 product overview 1 - 13 v dd pull-up resistor (typical value: 47 k w ) v dd pull-up enable data normal input output disable in/out analog input figure 1-9 . pin circuit type 6 (port 5) reset pull-up resistor (typical value: 200 k w ) v dd figure 1-10 . pin circuit type 7 ( reset reset )
S3C8465/c8469/p8469 electrical data 19- 1 1 9 electrical data overview in this chapter , S3C8465/c8469 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? input/output capacitance ? d.c. electrical characteristics ? a.c. electrical characteristics ? oscillation characteristics ? oscillation stabilization time ? data retention supply voltage in stop mode ? serial i/o timing characteristics ? uart timing characteristics in mode 0 ? a/d converter electrical characteristics ? zero crossing detector ? external memory timing characteristics
electrical data S3C8465/c8469/p8469 19- 2 table 19- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all input ports ? 0.3 to v dd + 0.3 v output voltage v o all output ports ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for ports 0, 2 ? 4, and 6 + 100 total pin current for ports 1 and 5 + 200 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 19- 2. input/output capacitance (t a = ? 40 c to 85 c, v dd = 0 v ) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are tied to v ss ? ? 10 pf output capacitance c out i/o capacitance c io
S3C8465/c8469/p8469 electrical data 19- 3 table 19- 3. d.c. electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit input high voltage v ih 1 v dd = 2.7 v to 5.5 v all port and reset 0.8 v dd ? v dd v v ih 2 v dd = 4.5 v to 5.5 v x in and x out v dd ? 1.0 input low voltage v il 1 v dd = 2.7 v to 5.5 v all ports and reset ? ? 0.2 v dd v v il 2 v dd = 4.5 v to 5.5 v x in and x out 0. 1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 ma all ports v dd ? 1.0 ? ? v output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 15 ma port s 1 ,5, and 6 ? 0.4 2.0 v v ol2 v dd = 4.5 v to 5.5 v i ol = 4 ma ports 0, 2, 3, and 4 input high leakage current i lih1 v in = v dd all input pins except i lih2 ? ? 1 a i lih2 v in = v dd x in , x out 20 input low leakage current i lil1 v in = 0 v all input pins except and i lil2 and reset ? ? ? 1 a i lil2 v in = 0 v x in , x out ? 20 output high leakage current i loh1 v out = v dd all output pins ? ? 2 a output low leakage current i lol v out = 0 v a ll output pins ? ? ? 2 a
electrical data S3C8465/c8469/p8469 19- 4 table 19- 3. d.c. electrical characteristics (continued) (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit pull-up resistor r p1 v dd = 5 v ; v in = 0 v 30 47 70 k w v dd = 3 v ; ports 0?6 30 ? 350 r p2 v dd = 5 v; v in = 0 v 100 200 400 v dd = 3 v; reset only 200 400 800 supply current ( n ote) i dd1 v dd = 4.5 v to 5.5 v run mode 12 mhz cpu clock ? 16 30 ma v dd = 2.7 v to 3.3 v 8 mhz cpu clock 5.5 12 i dd2 v dd = 4.5 v to 5.5 v idle mode 12 mhz cpu clock 3 6 v dd = 2.7 v to 3.3 v 8 mhz cpu clock 1 2.5 i dd3 v dd = 4.5 v to 5.5 v stop mode 1 5 a v dd = 2.7 v to 3.3 v stop mode note : supply current does not include current drawn through internal pull-up resistors , zcd, adc and external output current loads. table 19- 4. a.c. electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth , t intl ports 2, 3, and 4 ? 270 ? ns reset input low width t rsl input ? 1500 ? ns t inth t intl 0.8 v dd 0.2 v dd t rsl figure 19- 1. input timing measurement points
S3C8465/c8469/p8469 electrical data 19- 5 table 19-5 . oscillation characteristics (t a = ? 4 0 c + 85 c) oscillator clock circuit test condition min typ max unit main crystal or v dd = 4.5 v to 5.5 v 1 ? 12 mhz ceramic x in c1 c2 x out v dd = 2.7 v to 4.5 v 1 ? 8 external clock v dd = 4.5 v to 5.5 v 1 ? 12 mhz (main system) x in x out v dd = 2.7 v to 4.5 v 1 ? 8 cpu clock 1 khz main oscillator frequency 1 2 3 4 5 6 7 supply voltage (v) 8 khz 12 khz 2.7 v 5.5 v figure 19-2 . operating voltage range
electrical data S3C8465/c8469/p8469 19- 6 table 19- 6. oscillation stabilization time (t a = ? 4 0 c + 85 c, v dd = 2.7 v to 5.5 v) oscillator test condition min typ max unit main crystal f osc > 400 khz; ? ? 20 ms main ceramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 ms external clock (main system) x in input high and low width (t xh , t xl ) 25 ? 500 ns oscillator stabilization wait time t wait when released by a reset (1) ? 2 1 6 /f osc ? ms t wait when released by an interrupt (2) ? ? ? ms notes: 1. f osc is the oscillator frequency. 2. the duration of the oscillator stabilization wait time, t wait , when it is released by an interrupt is determined by the settings in the basic timer control register, btcon.
S3C8465/c8469/p8469 electrical data 19- 7 table 19- 7. data retention supply voltage in stop mode (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2 ? 5.5 v data retention supply current i dddr stop mode, v dddr = 2.0 v ? ? 5 a note : supply current does not include current drawn through internal pull-up resistors or external output current loads. note: t wait is the same as 4096 x 16 x 1/f osc . execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilzation time data retention mode t wait reset v dd normal operating mode figure 19-3 . stop mode release timing w hen initiated by a reset
electrical data S3C8465/c8469/p8469 19- 8 table 19- 8. serial i/o timing characteristics (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit sck cycle time t cky external sck source 1000 ? ? ns internal sck source 1000 sck high, low width t kh , t kl external sck source 500 ? ? internal sck source t kcy /2 ? 50 si setup time to sck low t sik external sck source 250 ? ? internal sck source 250 si hold time to sck high t ksi external sck source 400 ? ? internal sck source 400 output delay for sck to so t kso external sck source ? ? 300 internal sck source 250 note : " sck " means serial i/o clock frequency, " si " means serial data input, and " so " means serial data output. output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t kso t si k t ksi 0.8 v dd 0.2 v dd si so figure 19-4 . serial data transfer timing
S3C8465/c8469/p8469 electrical data 19- 9 table 1 9-9 . uart timing characteristics in mode 0 (10 mhz) (t a = ? 40 c to + 85 c, v dd = 2.7 v to 5.5 v, load capacitance = 80 pf) parameter symbol min typ max unit serial port clock cycle time t sck 500 t cpu 6 700 ns output data setup to clock rising edge t s1 300 t cpu 5 ? clock rising edge to input data valid t s2 ? ? 300 output data hold after clock rising edge t h1 t cpu ? 50 t cpu ? input data hold after clock rising edge t h2 0 ? ? serial port clock high, low level width t high, t low 200 t cpu 3 400 notes : 1. all timings are in nanoseconds (ns) and assume a 10-mhz cpu clock frequency. 2. the unit t cpu means one cpu clock period. 0.2 v dd 0.8 v dd t high t low t sck figure 19-5 . waveform for uart timing characteristics
electrical data S3C8465/c8469/p8469 19- 10 note: the symbols shown in this diagram are defined as follows: fsck serial port clock cycle time ts1 output data setup to clock rising edge ts2 clock rising edge to input data valid th1 output data hold after clock rising edge th2 input data hold after clock rising edge shift clock data out d0 d1 d2 d3 d4 d5 d6 d7 data in valid valid valid valid valid valid valid valid t sck t s1 t s2 t h1 t h2 figure 19-6 . a.c. timing waveform for the uart module
S3C8465/c8469/p8469 electrical data 19- 11 table 19-10. a/d converter electrical characteristics (t a = ? 40 c to + 85 c , v dd = 2.7 v to 5.5 v, v ss = 0 v ) parameter symbol test conditions min typ max unit resolution ? 10 ? bit total accuracy v dd = 5.12 v ? ? 3 lsb integral linearity error ile cpu clock = 10 mhz av ref = 5.12 v ? 2 differential linearity error dle av ss = 0 v ? 1 offset error of top eot 1 3 offset error of bottom eob 0.5 2 conversion time (1) t con 10-bit conversion 50 x 4/f osc (3) , f osc = 10 mhz 20 ? ? m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 ? ? m w analog reference voltage av ref ? 2.5 ? v dd v analog ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av ref = v dd = 5 v conversion time = 20 m s ? ? 10 m a analog block current (2) i adc av ref = v dd = 5 v conversion time = 20 m s 1 3 ma av ref = v dd = 3 v conversion time = 20 m s 0.5 1.5 ma av ref = v dd = 5 v when power down mode 100 500 na notes: 1. "conversion time" is the time required from the moment a conversion operation starts until it ends. 2. i adc is operating current during a/d conversion. 3. f osc is the main oscillator clock.
electrical data S3C8465/c8469/p8469 19- 12 table 19-11. zero crossing detector (t a = ? 40 c to + 85 c , v dd = 4.5 v to 5.5 v, v ss = 0 v ) parameter symbol test conditions min typ max unit zero-crossing detection input voltage v zc ac connection c = 0.1 m f 1.0 ? 3.0 vp-p zero-crossing detection accuracy v azc f zc = 60 hz (sine wave) v dd = 5 v f osc = 10 mhz ? ? 150 mv zero-crossing detection input frequency f zc ? 40 ? 200 hz 1/fzc v azc zcint ac input v az (p-p) figure 1 9-7 . zero crossing waveform diagram
S3C8465/c8469/p8469 electrical data 19- 13 table 19- 1 2 . external memory timing characteristics (8 mhz) (t a = ? 4 0 c to + 85 c, v dd = 2.7 v to 5.5 v) number symbol parameter normal timing (ns) min max 1 t da (as) address valid to as - delay 10 ? 2 t das (a) as - to address float delay 35 ? 3 t das (dr) as - to read data required valid ? 140 4 t was as low width 43.75 (35) ? 5 t da (ds) address float to ds 0 ? 6a t wds (read) ds (read) low width 156.25 (125) ? 6b t wds (write) ds (write) low width 81.25 (65) ? 7 t dds (dr) ds to read data required valid ? 80 8 t hds (dr) read data to ds - hold time 0 ? 9 t dds (a) ds - to address active delay 20 ? 10 t dds (as) ds - to as delay 30 ? 11 t ddo (ds) write data valid to ds (write) delay 10 ? 12 t drw (as) r/ w valid to as - delay 20 ? 13 t dds (dw) ds - to write data not valid delay 20 ? notes : 1. all times are in nanoseconds (ns) and assume an 8-mhz input frequency. 2. wait states add 100 ns to the time of numbers 3, 6a, 6b, and 7. 3. the values for t was and t wds that are shown in parentheses " ( ) " assume a 10-mhz input clock.
electrical data S3C8465/c8469/p8469 19- 14 r/ w (p2.2) port 0 dm (p2.3) port 1 as (p2.0) a8-a15, dm d0-d7 out a0-a7 12 3 9 10 8 1 4 11 2 5 7 13 6 d0-d7 in out ds (p2.1) figure 19-8 . external memory read and write timing (see table 19- 10 for a description of each timing point.)
S3C8465/c8469/p8469 mechanical data 20- 1 20 mechanical data overview the S3C8465/c8469/p8469 microcontrollers are available in a 64-sdip-750, 64-qfp-1420f package. note : dimensions are in millimeters. 0-15 #64 #33 #32 #1 17.00 0 .20 58.20 max 57.80 0 .20 0.45 0.10 1.00 0.10 1.778 0.51 min 3.30 0.30 4.10 0.20 5.08 max 19.05 (1.34) 64-sdip-750 0.25 + 0.10 - 0.05 figure 20-1. 64-sdip-750 package dimensions
mechanical data S3C8465/c8469/p8469 20- 2 64-qfp-1420f #64 20.00 0.20 23.90 0.30 14.00 0.20 17.90 0.30 #1 1.00 (1.00) 0.40 + 0.10 - 0.05 note : dimensions are in millimeters. 0.80 0.20 0.10 max 0.15 + 0.10 - 0.05 0-8 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.15 max figure 20-2. 64-qfp-1420f package dimensions
S3C8465/c8469/p8469 ks88p4632 otp 21- 1 21 s3p8469 otp overview the s3p8469 single-chip cmos microcontroller is the otp (one time programmable) version of the S3C8465/c8469 microcontroller. it has an on-chip otp rom instead of a masked rom. the eprom is accessed by serial data format. the s3p8469 is fully compatible with the S3C8465/c8469, both in function in d.c. electrical characteristics and in pin configuration. because of its simple programming requirements, the s3p8469 is ideal as an evaluation chip for the S3C8465/c8469.
ks88p4632 otp S3C8465/c8469/p8469 21- 2 p0.7/a15 p0.6/a14 p0.5/a13 p0.4/a12 p0.3/a11 p0.2/a10 p0.1/a9 p0.0/a8 p4.7/int11/tdg p4.6/int10/tcg p4.5/int9/tdck p4.4/int8/tcck p4.3/int7/capa sdat /p4.2/int6 sclk /p4.1/int5/rxd v dd /v dd v ss /v ss x out x in v pp /ea p4.0/int4 p3.7/txd reset reset /reset p3.6/so p3.5/si p3.4/ sck p3.3/t0ck p3.2/t0 p3.1/pwm1 p3.0/pwm0 p2.7/int3 p2.6/int2 S3C8465 s3c8469 (64-sdip) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p1.0/ad0 p1.1/ad1 p1.2/ad2 p1.3/ad3 p1.4/ad4 p1.5/ad5 p1.6/ad6 p1.7/ad7 p5.7/adc7 p5.6/adc6 p5.5/adc5 p5.4/adc4 p5.3/adc3 p5.2/adc2 p5.1/adc1 p5.0/adc0 av ss av ref p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p6.0 p2.0/ as p2.1/ ds p2.2/r/ w p2.3/ dm p2.4/zcd p2.5/buz 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 note: the bolds indicate an otp pin name. figure 21-1. s3p8469 pin assignments (64-sdip package)
S3C8465/c8469/p8469 ks88p4632 otp 21- 3 p0.0/a8 p4.7/int11/tdg p4.6/int10/tcg p4.5/int9/tdck p4.4/int8/tcck p4.3/int7capa sdat /p4.2/int6 sclk /p4.1/int5/rxd v dd /v dd v ss /v ss x out x in v pp /ea p4.0/int4 p3.7/txd reset reset /reset p3.6/so p3.5/si p3.4/ sck S3C8465 s3c8469 (64-qfp) top view p0.1/a9 p0.2/a10 p0.3/a11 p0.4/a12 p0.5/a13 p0.6/a14 p0.7/a15 p1.0/ad0 p1.1/ad1 p1.2/ad2 p1.3/ad3 p1.4/ad4 p1.5/ad5 p3.3/t0ck p3.2/t0 p3.1/pwm1 p3.0/pwm0 p2.7/int3 p2.6/int2 p2.5/buz p2.4/zcd p2.3/dm p2.2/r/ w p2.1/ds p2.0/as p6.0 p1.6/ad6 p1.7/ad7 p5.7/adc7 p5.6/adc6 p5.5/adc5 p5.4/adc4 p5.3/adc3 p5.2/adc2 p5.1/adc1 p5.0/adc0 av ss av ref p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 note: the bolds indicate an otp pin name. figure 21-2. s3p8469 pin assignments (64-qfp package)
ks88p4632 otp S3C8465/c8469/p8469 21- 4 table 21-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p4.2 sdat 14(7) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p4.1 sclk 15(8) i serial clock pin. input only pin. ea v pp 20(13) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is aplied, otp is in reading mode. (option) reset reset 23(16) i chip initialization v dd /v ss v dd /v ss 16(9)/17(10) ? logic power supply pin. v dd should be tied to +5 v during programming. note: ( ) means 64 qfp package. table 21-2. comparison of s3p8469 and S3C8465/c8469 features characteristic s3p8469 S3C8465/c8469 program memory 32k-byte eprom 16/32k-byte mask rom operating voltage (v dd ) 2.7 v to 5.5 v 2.7 v to 5.5 v otp programming mode v dd = 5 v, v pp (ea) = 12.5 v pin configuration 64 sdip/64 qfp 64 sdip/64 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (ea) pin of the s3p8469, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 21-3 below. table 21-3. operating mode selection criteria v dd v pp ( ea ) reg/ mem mem address (a15?a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.

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